
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity adder_n is
  generic ( 
    N: integer := 4
  ); 
  port (
    a_i    : in  std_logic_vector(N-1 downto 0);
    b_i    : in  std_logic_vector(N-1 downto 0);
    cin_i  : in  std_logic;
    y_o    : out std_logic_vector(N-1 downto 0);
    cout_o : out std_logic
  );
end adder_n;

architecture behav of adder_n is

  signal s_y : std_logic_vector(N downto 0);  

begin  -- behav
  
  s_y		<= ('0' & a_i) + ('0' & b_i) + cin_i;
  y_o		<= s_y(N-1 downto 0);
  cout_o	<= s_y(N);

end behav;

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